The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Semiconductor memory devices, such as random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), read only memory (ROM), programmable read only memory (PROM), electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and/or flash memory, include an integrated circuit (IC) that stores data and/or code. In certain applications, loss of any of the data may require a manufacturer and/or end user to replace the memory, which may be costly.
Referring now to FIG. 1, a memory control module 10 may control read/write operations to memory 14. The memory 14 includes memory banks 42-1, 42-2, . . . , and 42-x (collectively referred to as memory banks 42). Each memory bank 42 includes address rows 44-1, 44-2, . . . , and 44-y, referred to collectively as address rows 44, and address columns 46-1, 46-2, . . . , and 46-z (collectively referred to as address columns 46). Data bits are stored in the memory 14 according to specific address rows 44 and address columns 46 in each memory bank 42. Various methods are used to correct defects and improve memory yield. One method includes adding redundant address locations to the memory 14.
Referring now to FIGS. 2A and 2B, a memory repair device 64 may correct defects in the memory 14. The memory repair device 64 may be internal or external to a system that includes the memory 14. The memory repair 64 device may be implemented in a built-in self-test (BIST) that may include hardware or automatic test equipment (ATE) that may include software. The memory repair device 64 may command a memory repair sub-circuit 65 that may substitute redundant rows and/or columns of the memory 14 for defective address rows and/or columns.
The memory 14 includes memory banks 42, address rows 44, and address columns 46. Each memory bank 42 includes redundant address rows 58-1, 58-2, . . . , and 58-m (referred to collectively as redundant address rows 58), and/or redundant address columns 60-1, 60-2, . . . , and 60-n (referred to collectively as redundant address columns 60). Alternatively, the memory 14 may include redundant memory banks that may be substituted for defective banks.
Initially, the bit locations provided by the redundant address rows 58 and address columns 60 are not associated with a particular memory address. The memory repair sub-circuit 65 programs the redundant address rows 58 and address columns 60 to correspond to a specific memory address when a bit location associated with a memory address is found to be defective. The memory repair sub-circuit 65 may use hard repair or soft repair operations. Both hard and soft repair operations result in a redundant memory portion being used to store the data that would have otherwise been stored in the defective memory portion. Basically, the defective memory portion is remapped to the redundant memory portion either reversibly with a soft repair operation or irreversibly with a hard repair operation.
For a hard repair operation, the memory repair sub-circuit 65 may include fuses 63-1, 63-2, . . . , and 63-a, referred to collectively as fuses 63 (e.g. laser fuses and/or electrical fuses). The memory repair device 64 is connected to the memory repair sub-circuit 65 to determine a defective bit location associated with a memory address. The memory repair device 64 blows one or more of the fuses 63 (i.e. applies a laser or electrical current to the fuses 63) to form a new data path to the redundant location. Thereafter, data that is directed to be stored at the memory address may be stored in the redundant location. In this manner, an originally defective memory device may be repaired and also may be suitable to be used and/or sold.
In FIG. 2B, an exemplary memory repair sub-circuit 65 is shown in further detail. Signals 66-1, 66-2, . . . , and 66-b, referred to collectively as signals 66, are indicative of memory addresses of defective memory locations. For example, the signals 66 may be indicative of a defective address row. The memory repair sub-circuit 65 receives the signals 66 and a repair signal 67 from the memory repair device 64. The signals 66 are input to a redundant row decoder 68. The redundant row decoder 68 communicates with a redundant row 58-1 according to statuses of the fuses 63. As described above, the memory repair device 64 may be used to blow one or more of the fuses 63 to program the redundant row decoder 68 to associate a particular memory address with the redundant row 58-1. A similar approach may be used for redundant columns.
As mentioned, the above-described memory hard repair operation results in a permanent re-association of the memory address with the redundant location. The memory repair operation permanently changes the electrical behavior of the fuse element. In the case of a laser fuse, a high energy laser beam cuts through the fuse (i.e. a conductive fuse element is rendered non-conductive as a result of the memory repair operation). In the case of an electrical fuse, an electric pulse or pulses are applied to the fuse element. As a result, the fuse element changes from conductive to non-conductive or from non-conductive to conductive. A hard repair is performed once during manufacturing test, and is permanent for the lifetime of the memory.
For a soft repair, the memory repair device 64 remaps data paths by storing values in a remapping register of the memory repair sub-circuit 65 so that data is stored in memory 14 according to the remapping register. For example, the remapping register causes certain logic gates to be turned on and other logic gates to be turned off similar to blowing fuses in the hard repair operation. The registers, however, may be reset; and soft repairs may not permanently alter data paths to the memory 14.